Alliance Memory AS4C256M16D3LC-10BIN, SDRAM 4GByte Through Hole, 933MHz, 96-Pin 96-ball FBGA

The Alliance Memory Synchronous DRAM is based on a double data rate architecture to achieve high-speed operation and is internally configured as eight banks. The 4Gb chip is organized as 32Mbit x 16 I/Os across 8 banks. It supports double-data-rate transfer speeds up to 1866 Mb/sec per pin for general applications. The design complies with DDR3L standards, with all control and address inputs synchronized to a pair of externally supplied differential clocks.

Fully synchronous operation
8 internal banks for concurrent operation
Pipelined internal architecture
Precharge and active power down