Microchip Technology, DT100105
- RS Stock No.:
- 196-6403
- Mfr. Part No.:
- DT100105
- Brand:
- Microchip
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 196-6403
- Mfr. Part No.:
- DT100105
- Brand:
- Microchip
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| For Use With | Microchip’s eMPUs | |
| Kit Classification | Evaluation Board | |
| Featured Device | DT100105 | |
| Kit Name | MCP16502 EVALUATION BOARD | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
For Use With Microchip’s eMPUs | ||
Kit Classification Evaluation Board | ||
Featured Device DT100105 | ||
Kit Name MCP16502 EVALUATION BOARD | ||
The Microchip Technology MCP16502 (DT100105) series is an optimally integrated PMIC compatible with Microchip’s eMPUs
(embedded microprocessor units), requiring dynamic voltage Scaling (DVS), with the use of High-Performance mode (HPM). It is compatible with SAMA5DX and SAM9x6.The MCP16502 integrates four DC-DC buck regulators and two auxiliary LDOs and provides a comprehensive interfacing to the MPU, which includes an interrupt flag and a 1 MHz I2C interface, MPUs, supported by dedicated device variants which optimize the solution BOM.
(embedded microprocessor units), requiring dynamic voltage Scaling (DVS), with the use of High-Performance mode (HPM). It is compatible with SAMA5DX and SAM9x6.The MCP16502 integrates four DC-DC buck regulators and two auxiliary LDOs and provides a comprehensive interfacing to the MPU, which includes an interrupt flag and a 1 MHz I2C interface, MPUs, supported by dedicated device variants which optimize the solution BOM.
Four 1A Buck DC-DC Channels with 100% Maximum Duty Cycle Capability
Pin-Selectable Output Voltages for DDR Buck: 1.2V, 1.35V, 1.8V
MPU-Specific Built-In Default Channel Sequencing and nRSTO Assertion Delay
Pin-Selectable Output Voltages for DDR Buck: 1.2V, 1.35V, 1.8V
MPU-Specific Built-In Default Channel Sequencing and nRSTO Assertion Delay