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Cypress Semiconductor CY2304SXC-1 PLL Clock Buffer 8-Pin SOIC

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Cypress Semiconductor
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1 - 9£5.77
10 - 24£5.11
25 - 49£4.65
50 +£4.43

The CY2304 is a 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations.

Number of Elements per Chip1
Maximum Supply Current45 mA
Maximum Input Frequency133MHz
Mounting TypeSurface Mount
Package TypeSOIC
Pin Count8
Dimensions4.97 x 3.98 x 1.47mm
Maximum Operating Supply Voltage3.6 V
Maximum Operating Temperature+70 °C
Maximum Output Frequency133.3MHz
Minimum Operating Supply Voltage3 V
Minimum Output Frequency10MHz
Minimum Operating Temperature0 °C