Microchip DSPIC33CK256MP502-I/2N, Microprocessor dsPIC 16bit 100MHz 28-Pin UQFN
- RS Stock No.:
- 179-3985
- Mfr. Part No.:
- DSPIC33CK256MP502-I/2N
- Brand:
- Microchip
Currently unavailable
We don’t know if this item will be back in stock, it is being discontinued by the manufacturer.
- RS Stock No.:
- 179-3985
- Mfr. Part No.:
- DSPIC33CK256MP502-I/2N
- Brand:
- Microchip
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Family Name | dsPIC | |
| Data Bus Width | 16bit | |
| Maximum Frequency | 100MHz | |
| I/O Voltage | 3 → 3.6V | |
| Fabrication Technology | CMOS | |
| Mounting Type | Surface Mount | |
| Package Type | UQFN | |
| Pin Count | 28 | |
| Typical Operating Supply Voltage | 3.6 (Maximum) V | |
| Dimensions | 6 x 6 x 0.5mm | |
| Maximum Operating Temperature | +85 °C | |
| Automotive Standard | AEC-Q100 | |
| Minimum Operating Temperature | -40 °C | |
Select all | ||
|---|---|---|
Brand Microchip | ||
Family Name dsPIC | ||
Data Bus Width 16bit | ||
Maximum Frequency 100MHz | ||
I/O Voltage 3 → 3.6V | ||
Fabrication Technology CMOS | ||
Mounting Type Surface Mount | ||
Package Type UQFN | ||
Pin Count 28 | ||
Typical Operating Supply Voltage 3.6 (Maximum) V | ||
Dimensions 6 x 6 x 0.5mm | ||
Maximum Operating Temperature +85 °C | ||
Automotive Standard AEC-Q100 | ||
Minimum Operating Temperature -40 °C | ||
Microchip’s dsPIC33CK family of digital signal controllers (DSCs) features a single 100 MIPS 16-bit dsPIC® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors.
3.0V to 3.6V, -40ºC to +125ºC, DC to 100 MIPS
dsPIC33CK DSC Core:
Modified Harvard architecture with 16-bit data and 24-bit instructions
Code efficient (C and Assembly) CPU architecture designed for real-time applications
16 16-bit working registers
4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
Single-cycle, mixed-sign 32-bit MUL
Fast 6-cycle hardware 32/16 and 16/16 DIV
Dual 40-bit fixed point Accumulators (ACC) for DSP operations
Single-cycle MAC/MPY with dual data fetch and result write-back
Zero overhead looping support
dsPIC33CK DSC Core:
Modified Harvard architecture with 16-bit data and 24-bit instructions
Code efficient (C and Assembly) CPU architecture designed for real-time applications
16 16-bit working registers
4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
Single-cycle, mixed-sign 32-bit MUL
Fast 6-cycle hardware 32/16 and 16/16 DIV
Dual 40-bit fixed point Accumulators (ACC) for DSP operations
Single-cycle MAC/MPY with dual data fetch and result write-back
Zero overhead looping support