Microchip PIC, PIC Microcontroller, 128 kB Flash, 44-Pin TQFP
- RS Stock No.:
- 236-8945
- Mfr. Part No.:
- PIC18F47Q43-I/PT
- Brand:
- Microchip
Subtotal (1 tray of 160 units)*
£209.60
(exc. VAT)
£251.20
(inc. VAT)
FREE delivery for orders over £50.00
In Stock
- 160 unit(s) ready to ship
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Tray* |
---|---|---|
160 + | £1.31 | £209.60 |
*price indicative
- RS Stock No.:
- 236-8945
- Mfr. Part No.:
- PIC18F47Q43-I/PT
- Brand:
- Microchip
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Microchip | |
Family Name | PIC | |
Package Type | TQFP | |
Mounting Type | Surface Mount | |
Pin Count | 44 | |
Device Core | PIC | |
Program Memory Size | 128 kB | |
Program Memory Type | Flash | |
Select all | ||
---|---|---|
Brand Microchip | ||
Family Name PIC | ||
Package Type TQFP | ||
Mounting Type Surface Mount | ||
Pin Count 44 | ||
Device Core PIC | ||
Program Memory Size 128 kB | ||
Program Memory Type Flash | ||
The Microchip microcontroller features a 12-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced capacitive touch sensing, averaging, filtering, oversampling and threshold comparison. This family showcases a new 16-bit PWM module which provides dual independent outputs on the same time base. Additional features include vectored interrupt controller with fixed latency for handling interrupts, system bus arbiter, Direct Memory Access (DMA) capabilities, UART with support for asynchronous, DMX, DALI and LIN protocols, SPI, I2C, memory features like Memory Access Partition (MAP) to support users in data protection and bootloader applications, and Device Information Area (DIA), which stores factory calibration values to help improve temperature sensor accuracy.
C Compiler optimized RISC architecture
64 MHz clock input
62.5 ns minimum instruction cycle
Six Direct Memory Access (DMA) Controllers
User programmable source and destination sizes
Hardware and software triggered data transfers
Vectored Interrupt capability
Selectable high/low priority
Fixed interrupt latency of three instruction cycles
Programmable vector table base address
Backwards compatible with previous interrupt capabilities
127-Level deep hardware stack
Low current power on reset (POR)
Configurable Power up timer (PWRT)
Brown out reset (BOR)
low power BOR (LPBOR) Option
Windowed Watchdog timer (WWDT)
Watchdog Reset on too long or too
64 MHz clock input
62.5 ns minimum instruction cycle
Six Direct Memory Access (DMA) Controllers
User programmable source and destination sizes
Hardware and software triggered data transfers
Vectored Interrupt capability
Selectable high/low priority
Fixed interrupt latency of three instruction cycles
Programmable vector table base address
Backwards compatible with previous interrupt capabilities
127-Level deep hardware stack
Low current power on reset (POR)
Configurable Power up timer (PWRT)
Brown out reset (BOR)
low power BOR (LPBOR) Option
Windowed Watchdog timer (WWDT)
Watchdog Reset on too long or too
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