Microchip, 8bit 8 bit MCU, PIC18F45Q10 Microcontroller, 64MHz, 32 kb Flash, 40-Pin QFN
- RS Stock No.:
- 631-511
- Mfr. Part No.:
- PIC18F45Q10-E/MPVAO
- Brand:
- Microchip
Subtotal (1 box of 511 units)*
£609.623
(exc. VAT)
£731.752
(inc. VAT)
FREE delivery for orders over £50.00
Temporarily out of stock
- Shipping from 11 December 2025
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Units | Per unit | Per Box* |
---|---|---|
511 + | £1.193 | £609.62 |
*price indicative
- RS Stock No.:
- 631-511
- Mfr. Part No.:
- PIC18F45Q10-E/MPVAO
- Brand:
- Microchip
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Microchip | |
Family Name | PIC18F45Q10 | |
Package Type | QFN | |
Mounting Type | Surface Mount | |
Pin Count | 40 | |
Device Core | 8 bit MCU | |
Data Bus Width | 8bit | |
Program Memory Size | 32 kb | |
Maximum Frequency | 64MHz | |
Program Memory Type | Flash | |
Select all | ||
---|---|---|
Brand Microchip | ||
Family Name PIC18F45Q10 | ||
Package Type QFN | ||
Mounting Type Surface Mount | ||
Pin Count 40 | ||
Device Core 8 bit MCU | ||
Data Bus Width 8bit | ||
Program Memory Size 32 kb | ||
Maximum Frequency 64MHz | ||
Program Memory Type Flash | ||
- COO (Country of Origin):
- TH
The Microchip Microcontrollers feature analogue, core independent, and communication peripherals for a wide range of general purpose and low-power applications. These microcontroller devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They also offer a set of core independent peripherals such as Complementary Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross Detect (ZCD), Configurable Logic Cell (CLC), and Peripheral Pin Select (PPS), providing increased design flexibility and lower system cost.
C Compiler optimized RISC architecture
Programmable 2 level interrupt priority
31 level deep hardware stack
Three 8 bit timers with hardware limit timer
Four 16 bit timers
Low current power on reset
Power up timer
Brown out reset
Low power BOR option
Programmable 2 level interrupt priority
31 level deep hardware stack
Three 8 bit timers with hardware limit timer
Four 16 bit timers
Low current power on reset
Power up timer
Brown out reset
Low power BOR option