Toshiba 74HC32D, Quad 2-Input OR Logic Gate, 14-Pin SOIC
- RS Stock No.:
- 171-3389
- Mfr. Part No.:
- 74HC32D
- Brand:
- Toshiba
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 171-3389
- Mfr. Part No.:
- 74HC32D
- Brand:
- Toshiba
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Logic Function | OR | |
| Mounting Type | Surface Mount | |
| Number of Elements | 4 | |
| Number of Inputs per Gate | 2 | |
| Package Type | SOIC | |
| Pin Count | 14 | |
| Logic Family | 74HC | |
| Maximum Operating Supply Voltage | 6 V | |
| Maximum High Level Output Current | -5.2mA | |
| Maximum Propagation Delay Time @ Maximum CL | 135 ns @ 50 pF | |
| Minimum Operating Supply Voltage | 2 V | |
| Maximum Low Level Output Current | 5.2mA | |
| Width | 3.9mm | |
| Minimum Operating Temperature | -40 °C | |
| Dimensions | 8.95 x 3.9 x 1.38mm | |
| Height | 1.38mm | |
| Maximum Operating Temperature | +125 °C | |
| Length | 8.95mm | |
| Output Type | Buffer, CMOS | |
| Propagation Delay Test Condition | 50pF | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Logic Function OR | ||
Mounting Type Surface Mount | ||
Number of Elements 4 | ||
Number of Inputs per Gate 2 | ||
Package Type SOIC | ||
Pin Count 14 | ||
Logic Family 74HC | ||
Maximum Operating Supply Voltage 6 V | ||
Maximum High Level Output Current -5.2mA | ||
Maximum Propagation Delay Time @ Maximum CL 135 ns @ 50 pF | ||
Minimum Operating Supply Voltage 2 V | ||
Maximum Low Level Output Current 5.2mA | ||
Width 3.9mm | ||
Minimum Operating Temperature -40 °C | ||
Dimensions 8.95 x 3.9 x 1.38mm | ||
Height 1.38mm | ||
Maximum Operating Temperature +125 °C | ||
Length 8.95mm | ||
Output Type Buffer, CMOS | ||
Propagation Delay Test Condition 50pF | ||
The 74HC32D is a high speed CMOS 2-INPUT OR GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 2 stages including buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage.
High speed: tpd = 6 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 1.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V
Low power dissipation: ICC = 1.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V
