Nexperia 74AHC573PW,118 Octal-Bit Latch, Transparent D Type, 3 State, 20-Pin TSSOP
- RS Stock No.:
- 181-7365
- Mfr. Part No.:
- 74AHC573PW,118
- Brand:
- Nexperia
Stock information currently inaccessible
- RS Stock No.:
- 181-7365
- Mfr. Part No.:
- 74AHC573PW,118
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74AHC | |
| Latch Mode | Transparent | |
| Latching Element | D Type | |
| Number of Bits | 8 | |
| Number of Elements per Chip | 8 | |
| Number of Channels per Chip | 8 | |
| Output Type | 3 State | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Dimensions | 6.6 x 4.5 x 0.95mm | |
| Height | 0.95mm | |
| Length | 6.6mm | |
| Minimum Operating Supply Voltage | 2 V | |
| Minimum Operating Temperature | -40 °C | |
| Width | 4.5mm | |
| Maximum Operating Temperature | +125 °C | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74AHC | ||
Latch Mode Transparent | ||
Latching Element D Type | ||
Number of Bits 8 | ||
Number of Elements per Chip 8 | ||
Number of Channels per Chip 8 | ||
Output Type 3 State | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Dimensions 6.6 x 4.5 x 0.95mm | ||
Height 0.95mm | ||
Length 6.6mm | ||
Minimum Operating Supply Voltage 2 V | ||
Minimum Operating Temperature -40 °C | ||
Width 4.5mm | ||
Maximum Operating Temperature +125 °C | ||
Maximum Operating Supply Voltage 5.5 V | ||
- COO (Country of Origin):
- CN
The 74AHC573, 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The 74AHC573, 74AHCT573 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an output enable input (OE) are common to all latches. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74AHC573, 74AHCT573 is functionally identical to the 74AHC373, 74AHCT373, but has a different pin arrangement.