Toshiba 74VHC573FT 8bit-Bit Octal D Type Latch, Transparent D Type, 20-Pin TSSOP
- RS Stock No.:
- 171-3409
- Mfr. Part No.:
- 74VHC573FT
- Brand:
- Toshiba
Subtotal (1 pack of 25 units)*
£7.075
(exc. VAT)
£8.50
(inc. VAT)
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In Stock
- 2,425 unit(s) ready to ship
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Units | Per unit | Per Pack* |
---|---|---|
25 + | £0.283 | £7.08 |
*price indicative
- RS Stock No.:
- 171-3409
- Mfr. Part No.:
- 74VHC573FT
- Brand:
- Toshiba
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Toshiba | |
Logic Family | 74VHC | |
Latch Mode | Transparent | |
Latching Element | D Type | |
Number of Elements per Chip | 19 | |
Number of Bits | 8bit | |
Number of Channels per Chip | 8 | |
Polarity | Inverting | |
Mounting Type | Surface Mount | |
Package Type | TSSOP | |
Pin Count | 20 | |
Dimensions | 6.5 x 4.4 x 1mm | |
Height | 1mm | |
Length | 6.5mm | |
Minimum Operating Supply Voltage | 2 V | |
Maximum Operating Supply Voltage | 5.5 V | |
Width | 4.4mm | |
Minimum Operating Temperature | -40 °C | |
Automotive Standard | AEC-Q100 | |
Maximum Operating Temperature | +125 °C | |
Select all | ||
---|---|---|
Brand Toshiba | ||
Logic Family 74VHC | ||
Latch Mode Transparent | ||
Latching Element D Type | ||
Number of Elements per Chip 19 | ||
Number of Bits 8bit | ||
Number of Channels per Chip 8 | ||
Polarity Inverting | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Dimensions 6.5 x 4.4 x 1mm | ||
Height 1mm | ||
Length 6.5mm | ||
Minimum Operating Supply Voltage 2 V | ||
Maximum Operating Supply Voltage 5.5 V | ||
Width 4.4mm | ||
Minimum Operating Temperature -40 °C | ||
Automotive Standard AEC-Q100 | ||
Maximum Operating Temperature +125 °C | ||
The 74VHC573FT is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages
Wide operating temperature range: Topr = -40 to 125
High speed: fMAX = 180 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 1.0 V (max)
Pin and function compatible with the 74 series
(74AC/HC/AHC/LV etc.) 573 type.
High speed: fMAX = 180 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 1.0 V (max)
Pin and function compatible with the 74 series
(74AC/HC/AHC/LV etc.) 573 type.
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