Nexperia 74LVC574APW,112 Octal D Type Flip Flop IC, 3-State, 20-Pin TSSOP
- RS Stock No.:
- 178-7008
- Mfr. Part No.:
- 74LVC574APW,112
- Brand:
- Nexperia
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 178-7008
- Mfr. Part No.:
- 74LVC574APW,112
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | LVC | |
| Logic Function | D Type | |
| Input Type | Single Ended | |
| Output Type | 3 State | |
| Output Signal Type | Single Ended | |
| Triggering Type | Positive Edge | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Number of Elements per Chip | 8 | |
| Maximum Propagation Delay Time @ Maximum CL | 3.6 ns @ 2.7 V | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Dimensions | 6.6 x 4.5 x 0.95mm | |
| Minimum Operating Supply Voltage | 1.2 V | |
| Maximum Operating Temperature | +125 °C | |
| Minimum Operating Temperature | -40 °C | |
| Width | 4.5mm | |
| Height | 0.95mm | |
| Length | 6.6mm | |
| Propagation Delay Test Condition | 50pF | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family LVC | ||
Logic Function D Type | ||
Input Type Single Ended | ||
Output Type 3 State | ||
Output Signal Type Single Ended | ||
Triggering Type Positive Edge | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Number of Elements per Chip 8 | ||
Maximum Propagation Delay Time @ Maximum CL 3.6 ns @ 2.7 V | ||
Maximum Operating Supply Voltage 3.6 V | ||
Dimensions 6.6 x 4.5 x 0.95mm | ||
Minimum Operating Supply Voltage 1.2 V | ||
Maximum Operating Temperature +125 °C | ||
Minimum Operating Temperature -40 °C | ||
Width 4.5mm | ||
Height 0.95mm | ||
Length 6.6mm | ||
Propagation Delay Test Condition 50pF | ||
The 74LVC574A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an Output Enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options