Toshiba 74VHC273FT Octal D Type Flip Flop IC, CMOS, 20-Pin TSSOP
- RS Stock No.:
- 171-3546
- Mfr. Part No.:
- 74VHC273FT
- Brand:
- Toshiba
Discontinued
- RS Stock No.:
- 171-3546
- Mfr. Part No.:
- 74VHC273FT
- Brand:
- Toshiba
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Logic Family | 74VHC | |
| Logic Function | D Type | |
| Input Type | CMOS, TTL | |
| Output Type | CMOS | |
| Output Signal Type | Single Ended | |
| Triggering Type | Positive Edge | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Number of Elements per Chip | 8 | |
| Maximum Propagation Delay Time @ Maximum CL | 21.5 ns @ 50 pF | |
| Dimensions | 6.5 x 4.4 x 1mm | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Minimum Operating Temperature | -40 °C | |
| Minimum Operating Supply Voltage | 2 V | |
| Maximum Operating Temperature | +125 °C | |
| Automotive Standard | AEC-Q100 | |
| Length | 6.5mm | |
| Propagation Delay Test Condition | 50pF | |
| Height | 1mm | |
| Width | 4.4mm | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Logic Family 74VHC | ||
Logic Function D Type | ||
Input Type CMOS, TTL | ||
Output Type CMOS | ||
Output Signal Type Single Ended | ||
Triggering Type Positive Edge | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Number of Elements per Chip 8 | ||
Maximum Propagation Delay Time @ Maximum CL 21.5 ns @ 50 pF | ||
Dimensions 6.5 x 4.4 x 1mm | ||
Maximum Operating Supply Voltage 5.5 V | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 2 V | ||
Maximum Operating Temperature +125 °C | ||
Automotive Standard AEC-Q100 | ||
Length 6.5mm | ||
Propagation Delay Test Condition 50pF | ||
Height 1mm | ||
Width 4.4mm | ||
The 74VHC273FT is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLR input is held "L", the Q outputs are at a low logic level independent of the other inputs. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages
Wide operating temperature range: Topr = -40 to 125
High speed: fMAX = 165 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 0.8 V (max)
Pin and function compatible with the 74 series
(74AC/HC/AHC etc.) 273 type
High speed: fMAX = 165 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 0.8 V (max)
Pin and function compatible with the 74 series
(74AC/HC/AHC etc.) 273 type