Toshiba 74VHC74FT Dual D Type Flip Flop IC, CMOS, 14-Pin TSSOP
- RS Stock No.:
- 171-3463P
- Mfr. Part No.:
- 74VHC74FT
- Brand:
- Toshiba
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Units | Per unit |
|---|---|
| 50 + | £0.206 |
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- RS Stock No.:
- 171-3463P
- Mfr. Part No.:
- 74VHC74FT
- Brand:
- Toshiba
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Logic Family | 74VHC | |
| Logic Function | D Type | |
| Input Type | CMOS, TTL | |
| Output Type | CMOS | |
| Output Signal Type | Differential | |
| Triggering Type | Positive Edge | |
| Polarity | Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 14 | |
| Set/Reset | Preset | |
| Number of Elements per Chip | 2 | |
| Maximum Propagation Delay Time @ Maximum CL | 20 ns @ 50 pF | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Dimensions | 5 x 4.4 x 1mm | |
| Maximum Operating Temperature | +125 °C | |
| Height | 1mm | |
| Width | 4.4mm | |
| Propagation Delay Test Condition | 50pF | |
| Automotive Standard | AEC-Q100 | |
| Length | 5mm | |
| Minimum Operating Temperature | -40 °C | |
| Minimum Operating Supply Voltage | 2 V | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Logic Family 74VHC | ||
Logic Function D Type | ||
Input Type CMOS, TTL | ||
Output Type CMOS | ||
Output Signal Type Differential | ||
Triggering Type Positive Edge | ||
Polarity Inverting | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 14 | ||
Set/Reset Preset | ||
Number of Elements per Chip 2 | ||
Maximum Propagation Delay Time @ Maximum CL 20 ns @ 50 pF | ||
Maximum Operating Supply Voltage 5.5 V | ||
Dimensions 5 x 4.4 x 1mm | ||
Maximum Operating Temperature +125 °C | ||
Height 1mm | ||
Width 4.4mm | ||
Propagation Delay Test Condition 50pF | ||
Automotive Standard AEC-Q100 | ||
Length 5mm | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 2 V | ||
The 74VHC74FT is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input low. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Wide operating temperature range: Topr = -40 to 125
High speed: fMAX = 185 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28 % VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 1.0 V (max)
Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 74 type
High speed: fMAX = 185 MHz (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28 % VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Low noise: VOLP = 1.0 V (max)
Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 74 type