Nexperia 74HCT4094D,112 8-stage Surface Mount Shift Register HCT, 16-Pin SOIC
- RS Stock No.:
- 436-7717
- Mfr. Part No.:
- 74HCT4094D,112
- Brand:
- Nexperia
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 436-7717
- Mfr. Part No.:
- 74HCT4094D,112
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Package Type | SOIC | |
| Logic Function | Shift Register | |
| Number of Stages | 8 | |
| Logic Family | HCT | |
| Mounting Type | Surface Mount | |
| Operation Mode | Serial to Serial, Parallel | |
| Number of Elements | 1 | |
| Pin Count | 16 | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Dimensions | 10 x 4 x 1.45mm | |
| Triggering Type | Positive Edge | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Temperature | 125 °C | |
| Direction Type | Uni-Directional | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Package Type SOIC | ||
Logic Function Shift Register | ||
Number of Stages 8 | ||
Logic Family HCT | ||
Mounting Type Surface Mount | ||
Operation Mode Serial to Serial, Parallel | ||
Number of Elements 1 | ||
Pin Count 16 | ||
Minimum Operating Supply Voltage 4.5 V | ||
Maximum Operating Supply Voltage 5.5 V | ||
Dimensions 10 x 4 x 1.45mm | ||
Triggering Type Positive Edge | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Temperature 125 °C | ||
Direction Type Uni-Directional | ||
- COO (Country of Origin):
- TH
The 74HC4094, 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.
Simple control interface
I/O expansion
Asynchronous and synchronous load options
High frequency
Cascadable
LED drivers
Key applications
Displays
Control units