8SLVP1204ANLGI, Clock Buffer LVPECL, 4-Input, 16-Pin VFQFN
- RS Stock No.:
- 216-6229
- Mfr. Part No.:
- 8SLVP1204ANLGI
- Brand:
- Renesas Electronics
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 216-6229
- Mfr. Part No.:
- 8SLVP1204ANLGI
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Family | LVPECL | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVPECL | |
| Number of Clock Inputs | 4 | |
| Package Type | VFQFN | |
| Pin Count | 16 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Family LVPECL | ||
Logic Function Clock Buffer | ||
Input Signal Type LVPECL | ||
Number of Clock Inputs 4 | ||
Package Type VFQFN | ||
Pin Count 16 | ||
The Renesas Electronics 8SLVP1204 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1204 is characterized to operate from a 3.3V or 2.5V power supply.
Four low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS levels. See Applications Information, “Wiring the Differential Input to Accept Single-Ended Levels” (Figures 1A and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS levels. See Applications Information, “Wiring the Differential Input to Accept Single-Ended Levels” (Figures 1A and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V