854S006AGILF, Clock Buffer LVDS, 2-Input, 24-Pin SOIC
- RS Stock No.:
- 216-6214P
- Mfr. Part No.:
- 854S006AGILF
- Brand:
- Renesas Electronics
Bulk discount available
Subtotal 10 units (supplied in a tube)*
£176.50
(exc. VAT)
£211.80
(inc. VAT)
FREE delivery for orders over £50.00
Temporarily out of stock
- 65 unit(s) ready to ship
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Units | Per unit |
|---|---|
| 10 - 24 | £17.65 |
| 25 - 49 | £16.90 |
| 50 - 99 | £16.27 |
| 100 + | £14.93 |
*price indicative
- RS Stock No.:
- 216-6214P
- Mfr. Part No.:
- 854S006AGILF
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Family | LVDS | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVDS | |
| Number of Clock Inputs | 2 | |
| Package Type | SOIC | |
| Pin Count | 24 | |
Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Family LVDS | ||
Logic Function Clock Buffer | ||
Input Signal Type LVDS | ||
Number of Clock Inputs 2 | ||
Package Type SOIC | ||
Pin Count 24 | ||
The Renesas Electronics 854S006 is a low skew, high performance 1-to-6, Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept most standard differential input levels. The 854S006 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 854S006 ideal for those clock distribution applications demanding well defined performance and repeatability.
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature