5T9306NLGI, Clock Buffer LVDS, 1-Input, 8-Pin SOIC
- RS Stock No.:
- 216-6188
- Mfr. Part No.:
- 5T9306NLGI
- Brand:
- Renesas Electronics
Subtotal (1 unit)*
£9.31
(exc. VAT)
£11.17
(inc. VAT)
FREE delivery for orders over £50.00
Last RS stock
- Final 475 unit(s), ready to ship
Units | Per unit |
---|---|
1 + | £9.31 |
*price indicative
- RS Stock No.:
- 216-6188
- Mfr. Part No.:
- 5T9306NLGI
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Renesas Electronics | |
Logic Family | LVDS | |
Logic Function | Clock Buffer | |
Input Signal Type | LVDS | |
Number of Clock Inputs | 1 | |
Package Type | SOIC | |
Pin Count | 8 | |
Select all | ||
---|---|---|
Brand Renesas Electronics | ||
Logic Family LVDS | ||
Logic Function Clock Buffer | ||
Input Signal Type LVDS | ||
Number of Clock Inputs 1 | ||
Package Type SOIC | ||
Pin Count 8 | ||
The Renesas Electronics IDT5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9306 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs.
Guaranteed Low Skew < 40ps (max)
Very low duty cycle distortion < 125ps (max)
High speed propagation delay < 1.75ns (max)
Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
Up to 1GHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input interface
Selectable differential inputs to six LVDS outputs
Power-down mode
2.5V VDD
Available in VFQFPN package
Very low duty cycle distortion < 125ps (max)
High speed propagation delay < 1.75ns (max)
Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
Up to 1GHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input interface
Selectable differential inputs to six LVDS outputs
Power-down mode
2.5V VDD
Available in VFQFPN package