Renesas Electronics 8T49N242-999NLGI Clock Buffer 40-Pin VFQFN
- RS Stock No.:
- 250-3482
- Mfr. Part No.:
- 8T49N242-999NLGI
- Brand:
- Renesas Electronics
Subtotal (1 tray of 490 units)*
£2,364.74
(exc. VAT)
£2,837.59
(inc. VAT)
FREE delivery for orders over £50.00
In Stock
- 490 unit(s) ready to ship
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Units | Per unit | Per Tray* |
---|---|---|
490 + | £4.826 | £2,364.74 |
*price indicative
- RS Stock No.:
- 250-3482
- Mfr. Part No.:
- 8T49N242-999NLGI
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Renesas Electronics | |
Maximum Supply Current | 47 mA | |
Maximum Input Frequency | 875MHz | |
Mounting Type | Surface Mount | |
Package Type | VFQFN | |
Pin Count | 40 | |
Select all | ||
---|---|---|
Brand Renesas Electronics | ||
Maximum Supply Current 47 mA | ||
Maximum Input Frequency 875MHz | ||
Mounting Type Surface Mount | ||
Package Type VFQFN | ||
Pin Count 40 | ||
The Renesas Electronics frequency translator has one fractional-feedback PLL that can be used as a jitter attenuator and frequency translator. It is equipped with four integer output dividers, allowing the generation of up to four different output frequencies, ranging from 8kHz to 1GHz. These frequencies are completely independent of the input reference frequencies, and the crystal reference frequency. The outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels.
It accepts up to two differential or single-ended input clocks and a fundamental-mode crystal input
The internal PLL can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer
The device supports hitless reference switching between input clocks
The device monitors both input clocks for Loss of Signal and generates an alarm when an input clock failure is detected
The PLL has a register-selectable loop bandwidth from 0.2Hz to 6.4kHz
The device is programmable through an I2C interface
It also supports I2C master capability to allow the register configuration to be read from an external EEPROM
The internal PLL can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer
The device supports hitless reference switching between input clocks
The device monitors both input clocks for Loss of Signal and generates an alarm when an input clock failure is detected
The PLL has a register-selectable loop bandwidth from 0.2Hz to 6.4kHz
The device is programmable through an I2C interface
It also supports I2C master capability to allow the register configuration to be read from an external EEPROM
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