The CY23EP05 is a 2.5 V or 3.3 V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks. The -1H version operates up to 220 (200) MHz frequencies at 3.3 V (2.5 V), and has a higher drive strength than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23EP05 PLL enters a power-down mode when there are no rising edges on the REF input (< ∼2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. The CY23EP05 is available in different configurations. The CY23EP05-1 is the base part. The CY23EP05-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5 V input-tolerant applications.