Nexperia 74HCT373D,653, Octal Octal D Type Latch, 8-Bit Non-Inverting, 20-Pin SO-20
- RS Stock No.:
- 170-5429
- Mfr. Part No.:
- 74HCT373D,653
- Brand:
- Nexperia
Bulk discount available
Subtotal (1 pack of 25 units)*
£11.475
(exc. VAT)
£13.775
(inc. VAT)
FREE delivery for orders over £50.00
In Stock
- 100 unit(s) ready to ship
- Plus 25 unit(s) ready to ship from another location
- Plus 725 unit(s) shipping from 31 October 2025
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Units | Per unit | Per Pack* |
|---|---|---|
| 25 - 100 | £0.459 | £11.48 |
| 125 - 475 | £0.284 | £7.10 |
| 500 - 1225 | £0.271 | £6.78 |
| 1250 + | £0.216 | £5.40 |
*price indicative
- RS Stock No.:
- 170-5429
- Mfr. Part No.:
- 74HCT373D,653
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74HCT | |
| Logic Function | D Type | |
| Number of Elements per Chip | 8 | |
| Number of Channels per Chip | 8 | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SO-20 | |
| Pin Count | 20 | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Length | 13mm | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Height | 2.45mm | |
| Width | 7.6mm | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Temperature | +125 °C | |
| Dimensions | 13 x 7.6 x 2.45mm | |
Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74HCT | ||
Logic Function D Type | ||
Number of Elements per Chip 8 | ||
Number of Channels per Chip 8 | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type SO-20 | ||
Pin Count 20 | ||
Minimum Operating Supply Voltage 4.5 V | ||
Length 13mm | ||
Maximum Operating Supply Voltage 5.5 V | ||
Height 2.45mm | ||
Width 7.6mm | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Temperature +125 °C | ||
Dimensions 13 x 7.6 x 2.45mm | ||
- COO (Country of Origin):
- CN
The 74HC373, 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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