Alliance Memory AS4C8M16SA-7TCN, SDRAM 128Mbit Surface Mount, 166MHz, 3 V to 3.6 V, 54-Pin TSOP
- RS Stock No.:
- 230-8442P
- Mfr. Part No.:
- AS4C8M16SA-7TCN
- Brand:
- Alliance Memory
Bulk discount available
Subtotal 10 units (supplied in a tray)*
£20.20
(exc. VAT)
£24.20
(inc. VAT)
Stock information currently inaccessible
Units | Per unit |
---|---|
10 - 18 | £2.02 |
20 - 48 | £1.985 |
50 - 98 | £1.94 |
100 + | £1.775 |
*price indicative
- RS Stock No.:
- 230-8442P
- Mfr. Part No.:
- AS4C8M16SA-7TCN
- Brand:
- Alliance Memory
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
---|---|---|
Brand | Alliance Memory | |
Memory Size | 128Mbit | |
SDRAM Class | DDR | |
Organisation | 8M x 16 | |
Data Rate | 166MHz | |
Data Bus Width | 16bit | |
Address Bus Width | 12bit | |
Number of Bits per Word | 16bit | |
Maximum Random Access Time | 5.4ns | |
Number of Words | 8 M | |
Mounting Type | Surface Mount | |
Package Type | TSOP | |
Pin Count | 54 | |
Dimensions | 22.35 x 10.29 x 1.2mm | |
Height | 1.2mm | |
Length | 22.35mm | |
Maximum Operating Supply Voltage | 3.6 V | |
Width | 10.29mm | |
Minimum Operating Temperature | 0 °C | |
Minimum Operating Supply Voltage | 3 V | |
Maximum Operating Temperature | +70 °C | |
Select all | ||
---|---|---|
Brand Alliance Memory | ||
Memory Size 128Mbit | ||
SDRAM Class DDR | ||
Organisation 8M x 16 | ||
Data Rate 166MHz | ||
Data Bus Width 16bit | ||
Address Bus Width 12bit | ||
Number of Bits per Word 16bit | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 8 M | ||
Mounting Type Surface Mount | ||
Package Type TSOP | ||
Pin Count 54 | ||
Dimensions 22.35 x 10.29 x 1.2mm | ||
Height 1.2mm | ||
Length 22.35mm | ||
Maximum Operating Supply Voltage 3.6 V | ||
Width 10.29mm | ||
Minimum Operating Temperature 0 °C | ||
Minimum Operating Supply Voltage 3 V | ||
Maximum Operating Temperature +70 °C | ||
The Alliance Memory 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL