Cypress Semiconductor S27KL0641DABHI020, SDRAM 64Mbit Surface Mount, 100MHz, 24-Pin FBGA
- RS Stock No.:
- 193-8781P
- Mfr. Part No.:
- S27KL0641DABHI020
- Brand:
- Cypress Semiconductor
Bulk discount available
Subtotal 10 units (supplied in a tray)*
£32.80
(exc. VAT)
£39.40
(inc. VAT)
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Units | Per unit |
|---|---|
| 10 - 18 | £3.28 |
| 20 - 98 | £3.215 |
| 100 - 198 | £2.865 |
| 200 + | £2.805 |
*price indicative
- RS Stock No.:
- 193-8781P
- Mfr. Part No.:
- S27KL0641DABHI020
- Brand:
- Cypress Semiconductor
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Cypress Semiconductor | |
| Memory Size | 64Mbit | |
| SDRAM Class | DDR | |
| Organisation | 8M x 8 bit | |
| Data Rate | 100MHz | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 8bit | |
| Maximum Random Access Time | 36ns | |
| Number of Words | 8M | |
| Mounting Type | Surface Mount | |
| Package Type | FBGA | |
| Pin Count | 24 | |
| Dimensions | 8 x 6 x 0.8mm | |
| Height | 0.8mm | |
| Length | 8mm | |
| Maximum Operating Supply Voltage | 1.95 V | |
| Minimum Operating Temperature | -40 °C | |
| Width | 6mm | |
| Minimum Operating Supply Voltage | 1.7 V | |
| Maximum Operating Temperature | +85 °C | |
| Select all | ||
|---|---|---|
Brand Cypress Semiconductor | ||
Memory Size 64Mbit | ||
SDRAM Class DDR | ||
Organisation 8M x 8 bit | ||
Data Rate 100MHz | ||
Data Bus Width 8bit | ||
Number of Bits per Word 8bit | ||
Maximum Random Access Time 36ns | ||
Number of Words 8M | ||
Mounting Type Surface Mount | ||
Package Type FBGA | ||
Pin Count 24 | ||
Dimensions 8 x 6 x 0.8mm | ||
Height 0.8mm | ||
Length 8mm | ||
Maximum Operating Supply Voltage 1.95 V | ||
Minimum Operating Temperature -40 °C | ||
Width 6mm | ||
Minimum Operating Supply Voltage 1.7 V | ||
Maximum Operating Temperature +85 °C | ||
The Cypress Semiconductor 64 Mb device is a high speed CMOS using self-refresh dynamic RAM (DRAM) with a hyper bus interface. It refresh control logic within the device
manages the refresh operation on the RAM array and hyper bus has a low-signal-count, double data rate (DDR) interface that achieve high-speed read and write throughput.
manages the refresh operation on the RAM array and hyper bus has a low-signal-count, double data rate (DDR) interface that achieve high-speed read and write throughput.
100 MHz clock rate (200 MBps) at 3.0 V VCC
Sequential burst transaction
Sequential burst transaction