Toshiba 74HC573D 8bit-Bit Octal D Type Latch, Transparent D Type, 20-Pin SOIC
- RS Stock No.:
- 171-3106P
- Mfr. Part No.:
- 74HC573D
- Brand:
- Toshiba
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Subtotal 50 units (supplied on a continuous strip)*
£17.55
(exc. VAT)
£21.05
(inc. VAT)
FREE delivery for orders over £50.00
Last RS stock
- Final 40 unit(s), ready to ship
Units | Per unit |
|---|---|
| 50 - 90 | £0.351 |
| 100 - 490 | £0.313 |
| 500 - 990 | £0.306 |
| 1000 + | £0.298 |
*price indicative
- RS Stock No.:
- 171-3106P
- Mfr. Part No.:
- 74HC573D
- Brand:
- Toshiba
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Logic Family | 74HC | |
| Latch Mode | Transparent | |
| Latching Element | D Type | |
| Number of Elements per Chip | 19 | |
| Number of Bits | 8bit | |
| Number of Channels per Chip | 8 | |
| Polarity | Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SOIC | |
| Pin Count | 20 | |
| Dimensions | 13.1 x 7.5 x 2.25mm | |
| Height | 2.25mm | |
| Length | 13.1mm | |
| Maximum Operating Supply Voltage | 6 V | |
| Width | 7.5mm | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Temperature | +85 °C | |
| Minimum Operating Supply Voltage | 2 V | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Logic Family 74HC | ||
Latch Mode Transparent | ||
Latching Element D Type | ||
Number of Elements per Chip 19 | ||
Number of Bits 8bit | ||
Number of Channels per Chip 8 | ||
Polarity Inverting | ||
Mounting Type Surface Mount | ||
Package Type SOIC | ||
Pin Count 20 | ||
Dimensions 13.1 x 7.5 x 2.25mm | ||
Height 2.25mm | ||
Length 13.1mm | ||
Maximum Operating Supply Voltage 6 V | ||
Width 7.5mm | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Temperature +85 °C | ||
Minimum Operating Supply Voltage 2 V | ||
The 74HC573D is a high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gateC2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. These 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE).When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 13 ns (typ.) at VCC = 6.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V