Infineon NOR 8Mbit CFI Flash Memory 48-Pin TSOP, S29AL008J70TFI013
- RS Stock No.:
- 193-8785
- Mfr. Part No.:
- S29AL008J70TFI013
- Brand:
- Infineon
Subtotal (1 pack of 5 units)*
£9.48
(exc. VAT)
£11.375
(inc. VAT)
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- 970 unit(s) ready to ship
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Units | Per unit | Per Pack* |
|---|---|---|
| 5 + | £1.896 | £9.48 |
*price indicative
- RS Stock No.:
- 193-8785
- Mfr. Part No.:
- S29AL008J70TFI013
- Brand:
- Infineon
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Infineon | |
| Memory Size | 8Mbit | |
| Interface Type | CFI | |
| Package Type | TSOP | |
| Pin Count | 48 | |
| Organisation | 1M x 8 bit | |
| Mounting Type | Surface Mount | |
| Cell Type | NOR | |
| Minimum Operating Supply Voltage | 2.7 V | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Block Organisation | Asymmetrical | |
| Length | 12mm | |
| Height | 1.05mm | |
| Width | 18.4mm | |
| Dimensions | 18.4 x 12 x 1.05mm | |
| Series | S29AL | |
| Number of Words | 1M | |
| Minimum Operating Temperature | -40 °C | |
| Number of Bits per Word | 8bit | |
| Maximum Operating Temperature | +85 °C | |
| Automotive Standard | AEC-Q100 | |
| Maximum Random Access Time | 70ns | |
Select all | ||
|---|---|---|
Brand Infineon | ||
Memory Size 8Mbit | ||
Interface Type CFI | ||
Package Type TSOP | ||
Pin Count 48 | ||
Organisation 1M x 8 bit | ||
Mounting Type Surface Mount | ||
Cell Type NOR | ||
Minimum Operating Supply Voltage 2.7 V | ||
Maximum Operating Supply Voltage 3.6 V | ||
Block Organisation Asymmetrical | ||
Length 12mm | ||
Height 1.05mm | ||
Width 18.4mm | ||
Dimensions 18.4 x 12 x 1.05mm | ||
Series S29AL | ||
Number of Words 1M | ||
Minimum Operating Temperature -40 °C | ||
Number of Bits per Word 8bit | ||
Maximum Operating Temperature +85 °C | ||
Automotive Standard AEC-Q100 | ||
Maximum Random Access Time 70ns | ||
- COO (Country of Origin):
- TH
The S29AL008J is a 8 Mbit, 3.0 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch) and 48pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0, the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers.
The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. Duringerase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. Duringerase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.