The S25FS512S connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output(Single I/O or SIO) is supported as well as optional twobit (Dual I/O or DIO) and fourbit wide Quad I/O (QIO) or Quad PeripheralInterface (QPI) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, there are Double Data Rate(DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation,resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS512S devices at the higher clockrates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically.The S25FS512S products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. They are an excellent solution for systems with limited space, signal connections and power. They are ideal forcode shadowing to RAM, executing code directly (XIP) and storing reprogrammable data.