Nexperia 74HC595BZX 8-stage Surface Mount Shift Register/Latch 74HC DHXQFN16 p
- RS Stock No.:
- 243-4414P
- Mfr. Part No.:
- 74HC595BZX
- Brand:
- Nexperia
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Subtotal 50 units (supplied on a continuous strip)*
£8.70
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£10.45
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In Stock
- Plus 3,000 unit(s) shipping from 06 October 2025
- Plus 999,996,975 unit(s) shipping from 22 December 2025
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Units | Per unit |
|---|---|
| 50 - 75 | £0.174 |
| 100 - 225 | £0.132 |
| 250 - 975 | £0.13 |
| 1000 + | £0.081 |
*price indicative
- RS Stock No.:
- 243-4414P
- Mfr. Part No.:
- 74HC595BZX
- Brand:
- Nexperia
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Package Type | DHXQFN16 p | |
| Logic Function | Shift Register | |
| Number of Stages | 8 | |
| Logic Family | 74HC | |
| Mounting Type | Surface Mount | |
Select all | ||
|---|---|---|
Brand Nexperia | ||
Package Type DHXQFN16 p | ||
Logic Function Shift Register | ||
Number of Stages 8 | ||
Logic Family 74HC | ||
Mounting Type Surface Mount | ||
The Nexperia 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
CMOS low power dissipation
High noise immunity
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.