Toshiba 74HC245D, 18 Bus Transceiver, 8-Bit Non-Inverting, 20-Pin SOIC
- RS Stock No.:
- 171-3388
- Mfr. Part No.:
- 74HC245D
- Brand:
- Toshiba
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 171-3388
- Mfr. Part No.:
- 74HC245D
- Brand:
- Toshiba
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Logic Family | 74HC | |
| Number of Elements per Chip | 18 | |
| Number of Channels per Chip | 8 | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SOIC | |
| Pin Count | 20 | |
| Maximum High Level Output Current | -7.8mA | |
| Maximum Low Level Output Current | 7.8mA | |
| Maximum Propagation Delay Time @ Maximum CL | 180 ns @ 150 pF | |
| Maximum Operating Temperature | +125 °C | |
| Dimensions | 13.1 x 7.5 x 2.25mm | |
| Minimum Operating Temperature | -40 °C | |
| Width | 7.5mm | |
| Height | 2.25mm | |
| Maximum Operating Supply Voltage | 6 V | |
| Minimum Operating Supply Voltage | 2 V | |
| Propagation Delay Test Condition | 150pF | |
| Length | 13.1mm | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Logic Family 74HC | ||
Number of Elements per Chip 18 | ||
Number of Channels per Chip 8 | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type SOIC | ||
Pin Count 20 | ||
Maximum High Level Output Current -7.8mA | ||
Maximum Low Level Output Current 7.8mA | ||
Maximum Propagation Delay Time @ Maximum CL 180 ns @ 150 pF | ||
Maximum Operating Temperature +125 °C | ||
Dimensions 13.1 x 7.5 x 2.25mm | ||
Minimum Operating Temperature -40 °C | ||
Width 7.5mm | ||
Height 2.25mm | ||
Maximum Operating Supply Voltage 6 V | ||
Minimum Operating Supply Voltage 2 V | ||
Propagation Delay Test Condition 150pF | ||
Length 13.1mm | ||
The 74HC245D is high speed CMOS OCTAL BUS TRANSCEIVERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. They are intended for two-way asynchronous communication between data busses. The direction of data transmission is determined by the level of the DIR input The enable input( G )can be used to disable the device so that the busses are effectively isolated. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 10 ns (typ.) at VCC = 6.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V