Related Products
The integrated multi-DSPLL technology reduces the PCB footprint ...
Description:
The integrated multi-DSPLL technology reduces the PCB footprint and BOM by reducing the need for additional external components. Its 3 DSPLL can simultanously generate any combination of low jitter SyncE and IEEE-1588 compliant synchronization clocks.The Si5348 easily meets the jitter specifications of 25G, 40G and 100G PHYs, removing the need ...
Ultra-low additive jitter: 50 fs RMSBuilt-in LDOs for ...
Description:
Ultra-low additive jitter: 50 fs RMSBuilt-in LDOs for high PSRR performance and a reduction in external components. Up to 10 LVPECL outputs (model dependent)Multi-format inputs: LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOSWide frequency range: DC to 200 MHz, 725 MHz or 1250 MHz (model dependent)Output enable. Compatible with Si534x Clocks ...
Ultra-low additive jitter: 120 fs RMSBuilt-in LDOs for ...
Description:
Ultra-low additive jitter: 120 fs RMSBuilt-in LDOs for high PSRR performance and a reduction in external components. Up to 12 LVCMOS outputs (model dependent)LVCMOS inputDC to 200 MHz frequency range. Output enable. Compatible with Si534x Clocks and Si5xx Oscillators. The Silicon Labs Si5336x family are LVCMOS Fanout Clock Buffers that ...
Timekeepers, combine SRAM with up to 256 Kbytes ...
Description:
Timekeepers, combine SRAM with up to 256 Kbytes of memory, and a byte-wide interface along with a quartz-based very-low-power oscillator with a clock/calendar circuit to provide real-time data. Packages embed the battery and crystal.